This invention relates generally to microelectronic semiconductor devices, and more particularly to devices suited for very large scale integrated circuit (VLSI) applications.
The development of integrated semiconductor circuit design has been characterized by a trend toward increasing circuit densities. Various technologies have been devised to stimulate this trend. For example, transistor-transistor logic (TTL) was standard in digital equipment for a long time but has given way in many areas to N-channel MOS logic circuits because of their superiority in speed power product, packing density and ease of device fabrication. For these reasons, devices fabricated using these technologies are finding application primarily in memory and microprocessor circuits.
In one method that has been used to improve device isolation and achieve higher packing density and higher speed, a thin layer of oxide is grown on a substrate of single crystal silicon. A thin layer of polysilicon is then deposited on the oxide and standard photolithographic techniques are used to define an opening in a photoresist deposited thereon. The polysilicon and the oxide in the opening are subsequently removed by etching, exposing the surface of the single crystal silicon substrate. After removing the photoresist, an epitaxial layer is grown using a standard vapor phase epitaxy technique. The layer of polysilicon is required for proper seeding of the silicon layer on the oxide during epitaxial growth. In the resulting structure, the region in the epitaxial layer directly over the substrate will be a single crystal while the epitaxial region over the oxide will be polycrystalline.
One problem with this technique is that the oxide layer cannot be very thick, otherwise vapor phase epitaxial growth thereon is not possible and will cause problems in subsequent circuit fabrication. Another problem is that at conditions that are conductive to vapor phase epitaxial growth on the single crystal silicon region, the grain size of the polysilicon at the oxide substrate is usually very large, resulting in a very rough and granular surface and a very ragged interface between the polysilicon region and the single crystal region. Further, when the size of the opening is in the submicron range, a ragged interface will cause a higher leakage current and make it harder to define the subsequent geometry of the device.
One object of this invention is to provide a method of making an improved device particularly useful in the design of high density digital logic circuits. Another object is to provide a method of making a device having high speed, scalability and improved immunity to ionizing radiation.